Developed through the synergy of LeCroy’s electrical test and protocol test technologies, the PeRT³ test system combines the functions and features of a signal generator, bit error rate tester (BERT), protocol editor and data analysis system in one instrument. This combination provides the ability to fully automate testing of transceivers and electronic systems in a comprehensive manner that not only measures adherence to specifications, but also examines the entire performance envelope of the system under test.

Simple, intuitive interface for creating automated test scripts. With a few clicks, set up automated tests that initialize the DUT and record error rates while sweeping through any user defined range of jitter parameters. A graphical description of device margins along multiple parameter axes. Provides an instant picture of margins vs requirements of the parameters you are interested in. Plot error rates as a function of time. Immediately see when errors occur. Plot error rates as a function of any two other parameters such as jitter amplitude and frequency. Identify device sensitivities to specific jitter frequencies. Verify the device tolerance against the specifications. A full log of the stresses applied to the device under test and the resulting error rates, all logged against time. High-speed serial subsystem design and production is a sophisticated and delicate process of maintaining signal integrity from a transmitter that generates a signal passing through PCB traces, connectors and cables to a receiver at the other end. The process inevitably introduces deterioration in the signal in the form of increased jitter, electrical noise, reflections from connectors, amplitude fluctuations, timing distortions, and a host of other potential problems.

The design goal for the transmitter is to generate a strong, clean signal that can propagate through the channel and still deliver a quality signal at the other end. The design goal for the receiver is to be able to accurately decode weak signals with the accompanying noise and corruptions that occur in less than optimal connections. If both goals are accomplished, the result is a reliable and robust communications channel.

There is a set of specifications for each serial data standard (such as PCI Express, SAS, SATA, or USB 3.0) that is intended to ensure reliable signal transfer; at the electrical level through eye diagrams and bit error ratio testing, and at the protocol level through error detection schemes such as CRC.

Designers of serial transceivers, and users who are evaluating different designs from different vendors, need a more comprehensive test system that can explore the entire performance envelope of high-speed serial subsystem performance. Confirming that the device meets the industry specification is not always sufficient to distinguish between a device that barely passes the specification and a robust design that has significant margin to allow for real-world variations in conditions and signal quality.

Varying the type and amount of modulation introduced while counting the errors on the returning signal, the PeRT³ maps out the full performance envelope of the device under test along multiple dimensions. This provides not just a GO/NO-GO test, but quantifies the error margins and error susceptibilities of each new design or each tested device. Should failure occur during the test, the environment that caused the failure can be generated by simply highlighting the report, and the design engineer has an environmental setup built to troubleshoot.

The PeRT³ system is designed with simplicity in mind. Ready to use right out of the box, the PeRT³ system provides easy exploration of the entire envelope of serial transceiver performance and more complete characterization of each design in either a development test or automated test environment.

Pass/Fail information plotted against the stress parameters under test. See what happened for every test case—in real-time. Protocol enabling is a key advantage to using the PeRT³ test system rather than other test instruments currently on the market. The PeRT³ test system provides system control over the test configuration enabling automated testing. For example, the system can automatically command the remote device to enter a loop-back mode while a test is in progress.

The system can also generate test traffic that goes well beyond simple “pseudo random bit sequences” (PRBS) by using real data traffic. In addition, PeRT³ intelligently manages protocol-specific issues that cause unnecessary disruptions, such as the resynchronization of clocks in SATA through the use of the ALIGN primitive.

Finally, the system can use protocol level error testing as one means for evaluating the system performance, measuring protocol-specific errors such as CRC errors, R_ERR in SATA or ACK/NAK in PCI Express. 

Lien Documentations:http://www.lecroy.com/tm/products/SerialDataGenerators/PeRT3/

Specifications:

Generator Data Out
Bit Rate	622 Mb/s to 6 Gb/s
Data Format	NRZ, normal or inverted
Rise/Fall Time (20–80%)	34 psec typical
Programmable Rise/Fall Time	Yes
Max. Rise/Fall Time Mismatch	0.05 UI
Differential Amplitude Range	50 mV to 1.8V, 5 mV steps
Voltage Offset	-2 V to +2.5 V
Maximum AC Common Mode Voltage	20 mV
Maximum Intrinsic Jitter	< 20 psec typical
Tri-state Outputs	Yes
Electrical Idle Generation	Yes
SSC Support	Yes
Pre/De-emphasis Support	Yes
Return Loss SDD11 and S11	< -10 dB over entire frequency range
Generator Clock Out
Frequency Range	100 MHz to 6 GHz
Rise/Fall Time (20–80%)	34 psec typical
Voltage Rails	AC coupled
Jitter	1 psec RMS typical
Amplitude Range	CML
Sub-rate Clock	Divide by 1, or divide by any number between 8 and 511 (and multiplied by 1, 2, 4, or 8)
Jitter Stress	Yes
Protocols Supported
PCI Express	2.5 and 5 Gb/s
SAS	1.5, 3 and 6 Gb/s
SATA	1.5, 3 and 6 Gb/s
USB 3.0	5 Gb/s
Generator Jitter Stress
1.5 MHz – 100 MHz RMS Jitter	17 psec
10 KHz – 1.5 MHz RMS Jitter	17 psec
1.5 MHz – 100 MHz Dj P-P	240 psec
10 KHz – 1.5 MHz Dj P-P	240 psec
Periodic Jitter	Integrated and Calibrated
Sinusoidal Jitter	Integrated and Calibrated
Random Jitter	Integrated and Calibrated
Sine Interference	Integrated and Calibrated
Total Jitter	> 1 UI at high frequency, 10s of UIs at low frequency
External Jitter Injection	Yes
Error Detector Data In
Differential Amplitude Range	75 mV to 1.8 V
Format	NRZ